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February 2005 rev 1.3
Peak EMI Reducing Solution
Features
Generates an EMI optimized clocking signal at output. Input frequency - 14.31818 MHz. Frequency outputs: o o 120 MHz (modulated) - default. 72 MHz (modulated) or 48 MHz (modulated) selectable via I2C 1% Centre spread. Modulation rate: 40 KHz. Byte Write via I2C Supply voltage range 3.3V 0.3V. Available in 8-pin SOIC Package. Available in Commercial and Industrial Temperature ranges.
ASM3P2508A
The ASM3P2508A allows significant system cost savings by reducing the number of circuit board layers and shielding that are required to pass EMI regulations. The ASM3P2508A modulates the output of PLL in order to spread the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most clock generators. Lowering EMI by increasing a signal's bandwidth is called spread spectrum clock generation. The ASM3P2508A has a feature to power down the 72MHz/48MHz output by writing data into specific registers in the device via I2C. By writing a `0' into bit 1 of Byte 0, the PLL block generating 72 MHz / 48MHz can be powered down. Writing `0' into bit `7' of Byte 1 selects an output of 72 MHz on FOUT2CLK while a `1' at the same
Product Description
The ASM3P2508A is a versatile spread spectrum frequency modulator. The ASM3P2508A reduces electromagnetic interference (EMI) at the clock source.
location selects a 48 MHz clock output. However, the I2C block, crystal oscillator, and the PLL block generating 120MHz would be always running.
Block Diagram
VDD
XIN XOUT
Crystal Oscillator
PLL 1 FOUT1CLK (120 MHz)
SCL SDA
I2C Interface
PLL 2
FOUT2CLK (72 MHz / 48 MHz)
VSS
Alliance Semiconductor 2575 Augustine Drive * Santa Clara CA * Tel: 408-855-4900 * Fax: 408-855-4999 * www.alsc.com
February 2005 rev 1.3
Pin Configuration
XIN XOUT VDD FOUT1CLK
1 2 8 7
ASM3P2508A
VSS
SCL SDA FOUT2CLK
ASM3P2508A
3 4 6 5
Pin Description Pin Name
XIN XOUT VDD FOUT1CLK FOUT2CLK SDA SCL VSS
Type
I O P O O I/O I P Connection to crystal Connection to crystal
Description
Power supply for the analog and digital blocks Clock output-1 (120 MHz) - default Clock output-2 ( 72 MHz / 48 MHz) I2C Data I2C Clock Ground to entire chip
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Absolute Maximum Ratings Symbol
VDD, VIN TSTG TA Ts TJ TDV Storage temperature Operating temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD 22- A114-B)
ASM3P2508A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0 -65 to +125 0 to 70 260 150 2
Unit
V C C C C KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Operating Conditions Parameter
Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Serial Data Transfer Rate Output Driver Load Capacitance
Symbol
VDD TA FXIN
Condition / Description
3.3V 10%
Min
3 -10
Typ
3.3
Max
3.6 +70 14.31818
Unit
V C MHz
Standard Mode CL
10
100 15
Kb/s pF
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DC Electrical Characteristics
(Test Condition : All the parameters are measured at room temperature (25C) , unless otherwise stated)
ASM3P2508A
Parameter
Overall Supply Current, Dynamic Supply Current, Static All input pins
Symbol
Conditions / Description
Min
Typ
Max
Unit
Icc IDD
VDD =3.3V, FCLK =14.31818MHz, CL=15pF VDD = 3.3V, Software Power Down*
40 27
49 35
60 43
mA mA
High-Level Input VDD=3.3V VIH Voltage Low-Level Input VDD=3.3V VIL Voltage High-Level Input IIH Current Low-Level Input IIL Current (pull-up) Clock Outputs (FOUT1CLK, FOUT2CLK) High-Level Output Voltage Low-Level Output Voltage Output Impedance VOH VOL ZOH ZOL VDD= 3.3V, IOH = 20mA VDD= 3.3V, IOL = 20mA VO=0.5VDD; output driving high Vo=0.5VDD; output driving low
2.0 VSS-0.3 -1 -20
-36
VDD+0.3 0.8 1 -80
V V
A A
V V
2.5 0 -
29 27
3.3 0.4 -
* FOUT1CLK (120MHz) is functional and not loaded
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AC Electrical Characteristics Parameter
Rise Time Fall Time Clock Duty Cycle Frequency Deviation Jitter, Long Term
ASM3P2508A
Symbol
tr tf tD fD
Conditions/ Description
FOUT1CLK FOUT2CLK FOUT1CLK VO = 2.0V to 0.8V; CL = 15pF FOUT2CLK Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period VO = 0.8V to 2.0V; CL = 15pF Output Frequency =120MHz Output Frequency =72MHz /48 MHz On rising edges 500 uS apart at 2.5 V relative to an ideal clock, PLL B inactive * On rising edges 500 uS apart at 2.5 V relative to an ideal clock, PLL B active * From rising edge to next rising edge at 2.5 V, PLL B inactive * From rising edge to next rising edge at 2.5 V, PLL B active * Output active from power up, RUN Mode via Software Power Down
Min
640 440 660 460 45 -
Typ
680 480 720 520 2.73 1.78 45 165 110 390 125
Max
750 600 800 570 55 -
Unit
pS pS % %
Tj (LT)
pS pS PS
Jitter, peak to peak Clock Stabilization Time
Tj (OT)
tSTB
* CL = 15 pF, Fxin = 14.31818 MHz
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Typical Crystal Oscillator Circuit
ASM3P2508A
Crystal
R1 = 510Q
C1 = 27 pF
C2 = 27 pF
Typical Crystal Specifications
Fundamental AT cut parallel resonant crystal Nominal Frequency Frequency Tolerance Operating temperature range Storage Temperature Load Capacitance Shunt capacitance ESR 14.31818 MHz +/- 50 ppm or better at 25C -20C to +85C -40C to +85C 18pF 7 pF maximum 25 Q
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I2C Serial Interface Information
The information in this section assumes familiarity with I2C programming.
ASM3P2508A
How to program ASM3P2508A through I2C:
* * * * * * * * * * Master (host) sends a start bit. Master (host) sends the write address D4 (H). ASM3P2508A device will acknowledge. Master (host) sends the beginning byte location (N = 0, 1). ASM3P2508A device will acknowledge. Master (host) sends a byte count (X = 1,2) ASM3P2508A device will acknowledge. Master (host) starts sending byte N through byte (N+X - 1) ASM3P2508A device will acknowledge each byte one at a time. Master (host) sends a Stop bit.
How to Read from ASM3P2508A through I2C:
* * * * * * * * * * * Master (host) will send start bit. Master (host) sends the write address D4 (H). ASM3P2508A device will acknowledge. Master (host) sends the beginning byte location (N = 0, 1). ASM3P2508A device will acknowledge. Master (host) will send a separate start bit. Master (host) sends the read address D5 (H). ASM3P2508A device will acknowledge. ASM3P2508A device will send the byte count (X = 1, 2). Master (host) acknowledges. ASM3P2508A device sends byte N through byte (N+X - 1). Master (host) will need to acknowledge each byte. Master (host) will send a stop bit.
Controller (Host)
Start Bit Slave Address D4(H)
ASM3P2508A (slave/receiver)
* *
Controller (Host)
ACK Start Bit ACK Slave Address D4(H)
ASM3P2508A (slave/receiver)
Beginning byte location (=N) Byte count (=X) ACK Beginning byte (Byte N) ACK Next Byte (Byte N+1) ACK ---------Last Byte (Byte N+X-1) ACK Stop Bit
ACK Beginning Byte = N ACK Repeat start Slave address D5(H) ACK Byte Count (= X) ACK Beginning byte N ACK Next Byte N+1 ACK ---------Last Byte (Byte N+X-1) Not Acknowledge Stop Bit
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ASM3P2508A
57 (H). To put ASM3P2508A in `power down' mode, the
An example of a Byte Write via I2C to partially `power down' the device: ASM3P2508A can be partially `powered down' using bit 1 of Byte 0. The organization of the register bits for Byte `0' is given with default values below:
bit 1 of Byte 0 is to be changed to logic `0'. Hence writing a 55 (H) via I2C into Byte 0 would put the device in partial `power down' mode where the PLL block generating 72 MHz / 48 MHz would be powered down while I2C block, crystal oscillator, and the PLL block generating 120 MHz would still be active. The organization of the register bits is as below:
7
6
5
4
Bit 3
2
1
PLL2 1
0
PLL1 1
Resv Resv Resv Resv Resv Resv 0 1 0 1 0 1
7
Resv 0
6
Resv 1
5
Resv 0
4
Resv 1
Bit 3
Resv 0
2
Resv 1
1
PLL2 Enable 0
0
PLL1 Enable 1
Enable Enable
The function of partial power down of the device is of interest to us - that is bit 1 of Byte 0. In the default mode this bit is logic `1'. As such, the Byte 0 default value is
Byte 0
Power up default 48_MHz Mode Power down PLL with 72MHz Power down PLL with 48MHz 6F(H) 6F(H) 6D(H) 6D(H)
Byte 1
3F(H) BF(H) 3F(H) BF(H)
FOUT1CLK (MHz)
120 120 120 120
FOUT2CLK(MHz)
72 48 -
Figure showing a complete data transfer:
.
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Package Information 8-Pin SOIC Package
ASM3P2508A
E
H
D
A2
A C
e B
A 1
D
L
Dimensions Symbol Min
A1 A A2 B C D E e H L S 0.004 0.053 0.049 0.012 0.007
Inches Max
0.010 0.069 0.059 0.020 0.010
Millimeters Min Max
0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0 1.27 8 0.25 1.75 1.50 0.51 0.25
0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8
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Ordering Codes Part number
ASM3P2508A-08-ST ASM3P2508A-08-SR ASM3I2508A-08-ST ASM3I2508A-08-SR ASM3P2508AF-08-ST ASM3P2508AF-08-SR ASM3I2508AF-08-ST ASM3I2508AF-08-SR
ASM3P2508A
Marking
3P2508A 3P2508A 3I2508A 3I2508A 3P2508AF 3P2508AF 3I2508AF 3I2508AF
Package Configuration
8-PIN SOIC, TUBE 8-PIN SOIC, TAPE AND REEL 8-PIN SOIC, TUBE 8-PIN SOIC, TAPE AND REEL 8-PIN SOIC, TUBE, Pb Free 8-PIN SOIC, TAPE AND REEL, Pb Free 8-PIN SOIC, TUBE, Pb Free 8-PIN SOIC, TAPE AND REEL, Pb Free
Temperature
Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial
Device Ordering Information
ASM3P2508AF-08SR
OR - TSOT23 -6,T/R TT - TSSOP, TUBE TR - TSSOP, T/R VT - TVSOP, TUBE VR - TVSOP, T/R ST - SOIC, TUBE SR - SOIC, T/R QR - QFN, T/R QT - QFN, TRAY BT - BGA, TRAY BR - BGA, T/R UR - SOT-23,T/R
PIN COUNT LEAD FREE PART PART NUMBER X = Automotive (-40C to +125C) I = Industrial (-40C to +85C) P or n/c = Commercial (0C to +70C)
1 - reserved 2 - Non PLL based 3 - EMI Reduction 4 - DDR support products 5 - STD Zero Delay Buffer
6 - power management 7 - power management 8 - power management 9 - Hi performance 0 - reserved
Alliance Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
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ASM3P2508A
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: ASM3P2508A Document Version: v1.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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